Signal Integrity Symposium
Easing the Transition to Higher Speed Designs
Wednesday, December 9
9:00 a.m. - 4:30 p.m. PST
Hyatt Regency Santa Clara
5101 Great America Pkwy
Santa Clara, CA 95054
Join experts from Anritsu, Isola and AtaiTec as they show you how to successfully design high speed data hardware. This full day, complimentary Symposium takes a holistic approach on the topic of designing high data rate data links for signal integrity applications discussing design process, simulation and measurement. Attendees will be introduced to new methodologies and tools to avoid common pitfalls and improve the entire process.
Who should attend:
- Engineers and Engineering Managers active in high speed design.
This symposium is a must if you are:
- Transitioning or planning to transition to higher bit rates 28 Gb/s or higher
- Simulating high bit rate channels
- Exploring tools and methods to help measurements match simulations and get higher quality measurement results
- Interested in increasing high speed design confidence, reducing risk and improving schedule conformance